About me

I am a trained electrical engineer specializing in computer architecture and emerging technology–based computing. I earned both my Master’s and Ph.D. degrees in Electrical Engineering from the Indian Institute of Technology Bombay (IITB), Mumbai. Before and during my Master’s, I worked for five years in the Embedded & Real-Time Systems Lab (e-Yantra) at IITB, focusing on robotics and automation in self-driving and drone technologies. During my Ph.D., I had the opportunity to collaborate internationally, including a visiting scientist position at the Institute for Communication Technologies and Embedded Systems (ICE), RWTH Aachen University, Germany, and at PGI-7, Forschungszentrum Jülich, Germany.

My Ph.D. research, titled “Energy-Efficient Secure In-Memory Computing with RRAM”, focused on developing RRAM-based digital logic gates, multi-state architectures, Tsetlin machine architectures, and hardware security implementations. After completing my Ph.D., I continued as a postdoctoral researcher at PGI-7, Forschungszentrum Jülich, for one year.

Currently, I am building my startup, Ximplic, which focuses on developing advanced electronic design automation (EDA) tools for future computing technologies.

  • design icon

    Ximplic

    Design Automation for Future Computing Technologies.

Resume

Education

  1. Indian Institute of Technology (IIT) Bombay

    Dual Degree (M.Tech. + Ph.D.) | Electrical Engineering Specilization in Electonics Systems

    Thesis: Energy-efficient Secure In-memory computing with RRAM

    2018 — 2025

  2. Kurukshetra University, Kurukshetra

    B.Tech. | Electronics and Communication Engineering

    2012 — 2015

  3. Govt. Polytechnic Sirsa, Haryana

    Diploma | Electronics and Communication Engineering

    2009 — 2012

Experience

  1. Postdoctoral Researcher

    Forschungszentrum Julich GmbH

    Sep 2024 — Aug 2025

  2. Visiting Scientist

    Forschungszentrum Julich GmbH

    Feb 2023 — Dec 2023

  3. Visiting Scientist

    ICE at RWTH Aachen University

    Nov 2021 — Feb 2022

  4. Assistant Project Manager

    e-Yantra, IIT Bombay

    2015 — 2021

Publications

Journals

  1. Fritscher, M., Singh, S, Rizzi, T. et al. A flexible and fast digital twin for RRAM systems applied for training resilient neural networks. Sci Rep 14, 23695 (2024). doi: 10.1038/s41598-024-73439-z

  2. C. K. Jha, K. Qayyum, K. Coskun, S. Singh, S.,et al. "veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 9, pp. 4169-4179, Sept. 2024 doi: 10.1109/TCSI.2024.3424682

  3. Singh, S, et al. "Should we even optimize for execution energy? Rethinking mapping for MAGIC design style," IEEE ESL, vol. 15, no. 4, pp. 230–233, 2023. doi: 10.1109/LES.2023.3298740

  4. Parrini, L., Soliman, T., Hettwer, B., Borrmann, M. J., Singh, S, et al. "Neural In-Memory Checksums: An Error Detection and Correction Technique for In-Memory Computations."

    Accepted at Royal society - Philosophical Transactions A

  5. Singh, S, Paul, G., Bende, A., Kempen, T., Cüppers, F., Patkar, S., Rana, V., & Merchant, F. "Sequence Detection in Bilayer 1T1R RRAM Device with In-Memory Computing."

    Under review at Nature scientific report

Conferences

  1. Bende, A.*, Singh, S*, et al. "Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array," in 37th IEEE VLSID, 2024, pp. 565–570. doi: 10.1109/VLSID60093.2024.00100

  2. Singh, S, et al. "Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs," in ASP-DAC 2023, New York, NY, USA, 2023, p. 449–454. doi: 10.1145/3566097.3568348

  3. Singh, S, et al. "Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies," in 18th NanoArch, New York, NY, USA, 2024. doi: 10.1145/3611315.3633268

  4. Jha, C. K., Qayyum, K., Ç. Coşkun, Singh, S, et al. "veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing," Accepted in TCAS-I, 2024. doi: 10.1109/LES.2023.3298740

  5. Singh, S, et al. "In-Memory Mirroring: Cloning Without Reading," Accepted in IFIP/IEEE VLSI-SoC, 2024. doi: 10.48550/arXiv.2407.02921

  6. Singh, S, et al. "Finite State Automata Design using 1T1R ReRAM Crossbar," in 21st IEEE NEWCAS, 2023, pp. 1–5. doi: 10.1109/NEWCAS57931.2023.10198206

  7. Ghazal, O.*, Singh, S*, et al. "IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines," in ISLPED, 2023, pp. 1–6. doi: 10.1109/ISLPED58423.2023.10244315

  8. Parrini, L., Soliman, T., Hettwer, B., Borrmann, J. M., Singh, S, et al. "Error Detection and Correction Codes for Safe In-Memory Computations," ETS, 2024 (Accepted). doi: 10.48550/arXiv.2404.09818

  9. Singh, S, et al. "PA-PUF: A Novel Priority Arbiter PUF," in IFIP/IEEE VLSI-SoC, 2022, pp. 1–6. doi: 10.1109/VLSI-SoC54400.2022.9939642

  10. Rajendran, G., Zahoor, F., Singh, S, et al. "PR-PUF: A Reconfigurable Strong RRAM PUF," in IFIP/IEEE VLSI-SoC, 2023, pp. 1–6. doi: 10.1109/VLSI-SoC57769.2023.10321884

  11. Rajendran, G., Zahoor, F., Thakker, S. S., Singh, S, et al. "Harnessing Entropy: RRAM Crossbar-Based Unified PUF and RNG," in 37th IEEE VLSID, 2024, pp. 560–564. doi: 10.1109/VLSID60093.2024.00099

  12. Singh, S, et al. "Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar," in NEWCAS, 2023, pp. 1–5. doi: 10.1109/NEWCAS57931.2023.10198126

  13. Singh, S, et al. "MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory," in 29th ASP-DAC, 2024, pp. 282–287. doi: 10.1109/ASP-DAC58780.2024.10473924

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